The evaluation of electronic equipment hardness to space environment charged particle influence by single event effects in accordance with standard is carried out. Limitations of the current approach in radiation tolerance evaluation of modern electronic equipment are identified and its new variant of development is proposed. The stage of calculated and experimental evaluation allowing determining the radiation tolerance of functionally complex systems considering their recovery strategy is introduced. The comparative analysis of the spacecraft payload hardness obtained on the basis of the existent and proposed methods is provided.

The method of contactless heating of chips in electronic component base at radiation tests with use of powerful Infrared lasers is offered. The example of practical realization of a method, results of experiments with various samples of products, and also results of computer modeling of thermal processes in vacuum and on air are given. A method applicability from the point of view of temperature distribution inhomogeneity in the tested sample, heating speed and other factors are discussed.

The survey research of data on latent defects properties in gate insulator of MOS devices is conducted. Classification of latent defects, mechanisms of their origin and influence on irradiated samples properties are discussed. Dependences of MOS devices sensitivity to latent defects origin on a particles incidence angle are for the first time given. Amendments to the test methods on gate insulator breakdown regulated by operating normative documentation are offered.

Approach to the requirements establishment for integrated circuits hardness at heavy charged particles influence is offered. This method is based on comparing of probabilities of IC failures connected to reliability and the failures at heavy charged particles influence in the most severe operation conditions.

The results of irradiation experiments CMOS IC at a dose rate of 0.1 rad/s in electrical and passive modes are presented. There were two stages of surface defects formation, in both cases when irradiated with MOS transistors as the n-channel and p-channel.

The failure intensity in commercial memory chips in real flight data is compared with the calculation results received by means of new compact model. The parametric study of soft error rate calculation is presented. The benefits of new approach use are shown.

The approach to determination of CMOS chips dose margin is presented. This method is based on measurement a drain-gate characteristics of n- and p-channel transistors from chip composition at static gamma radiation impact. The presented approach allows to determine the dose margin by CMOS chips functioning for different supply voltage and to predict the dose level of chip functional failure.

Comparative calculation and experimental investigations on creep resistance and thermal cyclic behavior of two and three-layer single crystal emitter cladding of W-Nb, Mo-Nb and W alloys are executed. It is shown that using of three-layer cladding permits to ensure a long TFE lifetime and simultaneously to reduce its coast.

The fallacy of applying of RD V 319.03.31-99 provisions when calculating resistance test norms to special factors influence of difficult multielement electronic products is shown. It is offered to limit when calculating test norms of State standard RV 20.39.414-98, or to correct regulation document so that to make him applicable to calculation of test norms of multielement electronic products.

The hardware implementation and the software of diagnostic system of LIU-10 accelerator peripheral units operation with use of digital recorders of different types are presented.